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Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
FEATURES
* 4 differential LVHSTL compatible outputs * Selectable LVCMOS / LVTTL clock inputs for redundant and multiple frequency fanout applications * Maximum output frequency: 266MHz * Translates LVCMOS and LVTTL levels to LVHSTL levels * Output skew: 35ps (maximum) * Part-to-part skew: 150ps (maximum) * Propagation delay: 1.9ns (maximum) * 3.3V core, 1.8V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8525 is a low skew, high performance 1-to-4 LVCMOS-to-LVHSTL fanout buffer and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8525 has two selectable clock inputs that accept LVCMOS or LVTTL input levels and translate them to LVHSTL levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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Guaranteed output and part-to-part skew characteristics make the ICS8525 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK0 CLK1 0 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
GND CLK_EN CLK_SEL CLK0 nc CLK1 nc nc nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3
ICS8525
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
Type Description Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input. No connect. Positive supply pin. Output supply pins.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 6 5, 7, 8, 9 10 13, 18 Name GND CLK_EN CLK_SEL CLK0 CLK1 nc VDD VDDO Power Input Input Input Input Unused Power Power Pullup Pulldown Pulldown Pulldown
11, 12 nQ3, Q3 Output Differential output pair. LVHSTL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVHSTL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVHSTL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVHSTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
Inputs Outputs Selected Source CLK0 CLK1 CLK0 Q0:Q3 Disabled; LOW Disabled; LOW Enabled nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 CLK1 Enabled Enabled After CLK_EN switches, the clock ooutputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Disabled
CLK0, CLK1
Enabled
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK0 or CLK1 0 1 Q0:Q3 LOW HIGH Outputs nQ0:nQ3 HIGH LOW
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 73.2C/W (0 lfpm) -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 Maximum 3.465 2.0 50 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VIH Parameter Input High Voltage CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1, CLK_SEL CLK_EN CLK0, CLK1, CLK_SEL CLK_EN Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Typical Maximum 3.765 3.765 1.3 0.8 150 5 Units V V V V A A A A
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Parameter Test Conditions Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX Output Crossover Voltage Peak-to-Peak VSWING Output Voltage Swing NOTE 1: Outputs terminated with 50 to GND.
8525BG
Symbol
Minimum 1 0 40% x (VOH-VOL) + VOL 0.75
Typical
Maximum 1.2 0.4 60% x (VOH-VOL) + VOL 1.25
Units V V V V
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
Test Conditions 266MHz Minimum 1.0 Typical Maximum 266 1.9 35 150 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 700 700 Units MHz ns ps ps ps ps %
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol fMAX tPD Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time
t sk(o) t sk(pp)
tR tF
odc Output Duty Cycle 45 50 55 All parameters measured at 266MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDDO VDD
SCOPE
Qx
LVHSTL
VDD = 3.3V 5% VDDO = 1.8V 0.2V
nQx
GND = 0V
OUTPUT LOAD TEST CIRCUIT
nQx
Qx
nQy Qy
tsk(o)
OUTPUT SKEW
nQx PART 1 Qx
nQy PART 2 Qy
tsk(pp)
PART-TO-PART SKEW
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
80% 80% V 20% 20% t t
SWING
Clock Inputs and Outputs
R
F
INPUT AND OUTPUT RISE AND FALL TIME
CLK0, CLK1
nQ0:nQ3 Q0 :Q3
t
PD
PROPAGATION DELAY
nQ0:nQ3 Q0:Q3
Pulse Width t t odc = t
PW PERIOD
PERIOD
odc & tPERIOD
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8525. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8525 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 4 x 32mW = 128mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 128mW = 301.25mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.301W * 66.6C/W = 90.05C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE q
JA
FOR
20-PIN TSSOP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 8.
VDDO
Q1
VOUT RL 50
FIGURE 8 - LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V
OH_MAX
/R ) * (V
L DDO_MAX
-V
OH_MAX
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DDO_MAX
-V
OL_MAX
Pd_H = (1.2V/50) * (2V - 1.2V) = 19.2mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0 114.5C/W 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8525 is: 484
8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Symbol N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
8525BG
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REV. B MAY 6, 2002
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Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
Marking Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel Count 72 per tube 2500 Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8525BG ICS8525BG-T ICS8525BG ICS8525BG
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8525BG
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REV. B MAY 6, 2002
Integrated Circuit Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Updated Figure 1, CLK_EN Timing Diagram. Updated Figure 1, CLK_EN Timing Diagram. Features section, deleted 1.8V in Bullet 1 and 4. Date 10/17/01 11/2/01 5/6/02
Rev B B B
Table
Page 3 3 1
8525BG
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